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@ -1,7 +1,7 @@ |
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/// @ref core |
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/// @ref core |
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/// @file glm/detail/type_tvec4_simd.inl |
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/// @file glm/detail/type_tvec4_simd.inl |
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#if GLM_ARCH & GLM_ARCH_SSE2 |
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#if GLM_ARCH & GLM_ARCH_SSE2_FLAG |
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namespace glm{ |
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namespace glm{ |
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namespace detail |
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namespace detail |
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@ -72,7 +72,7 @@ namespace detail |
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} |
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} |
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}; |
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}; |
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# if GLM_ARCH & GLM_ARCH_AVX2 |
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# if GLM_ARCH & GLM_ARCH_AVX2_FLAG |
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template <typename T, precision P> |
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template <typename T, precision P> |
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struct compute_vec4_and<T, P, true, 64> |
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struct compute_vec4_and<T, P, true, 64> |
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{ |
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{ |
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@ -96,7 +96,7 @@ namespace detail |
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} |
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} |
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}; |
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}; |
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# if GLM_ARCH & GLM_ARCH_AVX2 |
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# if GLM_ARCH & GLM_ARCH_AVX2_FLAG |
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template <typename T, precision P> |
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template <typename T, precision P> |
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struct compute_vec4_or<T, P, true, 64> |
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struct compute_vec4_or<T, P, true, 64> |
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{ |
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{ |
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@ -120,7 +120,7 @@ namespace detail |
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} |
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} |
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}; |
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}; |
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# if GLM_ARCH & GLM_ARCH_AVX2 |
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# if GLM_ARCH & GLM_ARCH_AVX2_FLAG |
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template <typename T, precision P> |
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template <typename T, precision P> |
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struct compute_vec4_xor<T, P, true, 64> |
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struct compute_vec4_xor<T, P, true, 64> |
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{ |
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{ |
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@ -144,7 +144,7 @@ namespace detail |
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} |
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} |
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}; |
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}; |
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# if GLM_ARCH & GLM_ARCH_AVX2 |
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# if GLM_ARCH & GLM_ARCH_AVX2_FLAG |
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template <typename T, precision P> |
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template <typename T, precision P> |
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struct compute_vec4_shift_left<T, P, true, 64> |
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struct compute_vec4_shift_left<T, P, true, 64> |
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{ |
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{ |
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@ -168,7 +168,7 @@ namespace detail |
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} |
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} |
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}; |
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}; |
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# if GLM_ARCH & GLM_ARCH_AVX2 |
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# if GLM_ARCH & GLM_ARCH_AVX2_FLAG |
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template <typename T, precision P> |
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template <typename T, precision P> |
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struct compute_vec4_shift_right<T, P, true, 64> |
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struct compute_vec4_shift_right<T, P, true, 64> |
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{ |
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{ |
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@ -192,7 +192,7 @@ namespace detail |
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} |
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} |
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}; |
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}; |
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# if GLM_ARCH & GLM_ARCH_AVX2 |
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# if GLM_ARCH & GLM_ARCH_AVX2_FLAG |
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template <typename T, precision P> |
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template <typename T, precision P> |
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struct compute_vec4_bitwise_not<T, P, true, 64> |
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struct compute_vec4_bitwise_not<T, P, true, 64> |
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{ |
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{ |
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@ -248,7 +248,7 @@ namespace detail |
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data(_mm_set1_ps(s)) |
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data(_mm_set1_ps(s)) |
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{} |
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{} |
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# if GLM_ARCH & GLM_ARCH_AVX |
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# if GLM_ARCH & GLM_ARCH_AVX_FLAG |
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template <> |
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template <> |
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GLM_FUNC_QUALIFIER GLM_CONSTEXPR_SIMD tvec4<double, lowp>::tvec4(double s) : |
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GLM_FUNC_QUALIFIER GLM_CONSTEXPR_SIMD tvec4<double, lowp>::tvec4(double s) : |
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data(_mm256_set1_pd(s)) |
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data(_mm256_set1_pd(s)) |
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@ -280,7 +280,7 @@ namespace detail |
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data(_mm_set1_epi32(s)) |
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data(_mm_set1_epi32(s)) |
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{} |
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{} |
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# if GLM_ARCH & GLM_ARCH_AVX2 |
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# if GLM_ARCH & GLM_ARCH_AVX2_FLAG |
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template <> |
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template <> |
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GLM_FUNC_QUALIFIER GLM_CONSTEXPR_SIMD tvec4<int64, lowp>::tvec4(int64 s) : |
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GLM_FUNC_QUALIFIER GLM_CONSTEXPR_SIMD tvec4<int64, lowp>::tvec4(int64 s) : |
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data(_mm256_set1_epi64x(s)) |
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data(_mm256_set1_epi64x(s)) |
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@ -350,4 +350,4 @@ namespace detail |
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*/ |
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*/ |
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}//namespace glm |
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}//namespace glm |
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#endif//GLM_ARCH & GLM_ARCH_SSE2 |
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#endif//GLM_ARCH & GLM_ARCH_SSE2_FLAG |
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